Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS leve

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER 1:2 3GHZ 16TSSOP 集成电路（IC） 时钟缓冲器，驱动器

Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes Page：23 Pages

Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS leve

Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes Page：23 Pages

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels.