丝印代码：VHC74；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Dual D-Type Flip-Flop with Preset and Clear General The 74VHC74FT is an advanced high speed CMOS D-FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14TSSOP 集成电路（IC） 触发器

74VHC CMOS logic IC series

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The 74VHC74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. ■ HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at

Dual D-Type Flip-Flop with Set and Reset

The MC74VHC74 is an advanced high speed CMOS D–type flip–flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The 74VHC74 is an advanced high-speed CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. ■ HIGH SPEED: fMAX = 170 MHz (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at

Dual D-Type Flip-Flop with Set and Reset

The MC74VHC74 is an advanced high speed CMOS D–type flip–flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output

Dual D-Type Flip-Flop with Set and Reset

The MC74VHC74 is an advanced high speed CMOS D–type flip–flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output