LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE HIGH PERFORMANCE

DESCRIPTION The 74LVC86A is a low voltage CMOS QUAD EXCLUSIVE OR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. It can be interfaced to 5V signal environment for

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC GATE XOR 4CH 2-INP 14TSSOP 集成电路（IC） 门和反相器

Quad 2-input EXCLUSIVE-OR gate

DESCRIPTION The 74LVC86 is a high-performance, low-power, low-voltage Si-gate CMOS device that is pin and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5

Quad 2-input exclusive OR gate

DESCRIPTION The 74LVC86A is a high-performance, low-power, low-voltage Si-gate CMOS device that is pin and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3

LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE HIGH PERFORMANCE

DESCRIPTION The 74LVC86A is a low voltage CMOS QUAD EXCLUSIVE OR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. It can be interfaced to 5V signal environment for

Low-Voltage CMOS Quad 2-Input XOR Gate

The 74LVC86A is a high performance, quad 2−input XOR gate operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 V allows 74L

QUADRUPLE 2-INPUT EXCLUSIVE OR GATES

Description The 74LVC86A provides four independent 2-input exclusive OR gates. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for parti