Low-Voltage CMOS Octal Buffer Flow Through Pinout

Low-Voltage CMOS Octal Transparent Latch With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC573A is a high performance, non−inverting octal transparent latch operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to inp

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

OCTAL TRANSPARENT D-TYPE LATCH WITH 3 STATE OUTPUTS

Description The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to

OCTAL D-TYPE LATCH HIGH PERFORMANCE

DESCRIPTION The 74LVC573A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. ■ 5V TOLERANT INPUTS ■ HIGH SPEED: tPD = 6.8ns (MAX.) a

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

1. General description The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

Standard-logic

The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight •Supply Voltage Range from 1.65V to 3.6V \n•Sinks or Sources 24mA at VCC = 3V \n•CMOS Low Power Consumption \n•IOFF Supports Partial-Power Down Operation \n•Inputs or Outputs Accept Up to 5.5V \n•Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications \n•Schmitt Trigger Action at ;

OCTAL D-TYPE LATCH HIGH PERFORMANCE

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

1. General description The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

1. General description The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

Low-Voltage CMOS Octal Buffer Flow Through Pinout

Low-Voltage CMOS Octal Transparent Latch With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC573A is a high performance, non−inverting octal transparent latch operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to inp

OCTAL D-TYPE LATCH HIGH PERFORMANCE

DESCRIPTION The 74LVC573A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. ■ 5V TOLERANT INPUTS ■ HIGH SPEED: tPD = 6.8ns (MAX.) a

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC573A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

1. General description The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

Octal D-type transparent latch with 5 V tolerantinputs/outputs; 3-state

The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches.\n When LE is HIGH, data at the Dn input • 5 V tolerant inputs/outputs, for interfacing with 5 V logic\n• Supply voltage range from 1.2 V to 3.6 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• High-impedance when VCC = 0 V\n• Flow-through pinout architecture\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 ;

OCTAL TRANSPARENT D-TYPE LATCH WITH 3 STATE OUTPUTS

Description The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to

OCTAL TRANSPARENT D-TYPE LATCH WITH 3 STATE OUTPUTS

Description The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to

OCTAL D-TYPE LATCH HIGH PERFORMANCE

DESCRIPTION The 74LVC573A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. ■ 5V TOLERANT INPUTS ■ HIGH SPEED: tPD = 6.8ns (MAX.) a

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

文件：161.56 Kbytes Page：20 Pages

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

文件：261.12 Kbytes Page：16 Pages

封装/外壳：20-VFQFN 裸露焊盘 包装：管件 描述：IC TRANSPARENT LATCH 20DHVQFN 集成电路（IC） 锁存器

封装/外壳：20-XFQFN 裸露焊盘 包装：管件 描述：IC TRANSPARENT LATCH 20DHXQFN 集成电路（IC） 锁存器

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

文件：261.12 Kbytes Page：16 Pages

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

文件：261.12 Kbytes Page：16 Pages

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

文件：261.12 Kbytes Page：16 Pages

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

文件：127.46 Kbytes Page：9 Pages