74LVC374: Low Voltage CMOS Octal D Flip-Flop

The 74LVC374A is a high performance, non-inverting octal D-type flip-flop operating from a 1.2 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5 Designed for 1.2 to 3.6 V VCC Operation\n5 V Tolerant − Interface Capability With 5 V TTL Logic\nSupports Live Insertion and Withdrawal\nIOFF Specification Guarantees High Impedance When VCC = 0 V\n24 mA Output Sink and Source Capability\nNear Zero Static Supply Current in All Three Logic States (10;

Octal D-Type Positive Edge-Triggered Flip-Flop with 3-State Outputs

The 74LVC374A is an 8-bit D-type positive edge-triggered flip-flop with 3-state outputs that is designed for 1.2V to 3.6V VCC operation. \nThe device is provided with a clock (CP) input and an output enable (OE) input. When data at the Dn inputs suffices for setup and hold time purposes, data can be • Wide Operating Voltage Range: 1.2V to 3.6V\n• Input and Output Interface Capability to 5V System Environment\n• +24mA/-24mA Output Current\n• CMOS Low Power Dissipation\n• Support Partial Power-Down Mode\n• Outputs in High-Impedance State when VCC = 0V\n• -40℃ to +125℃ Operating Temperature Range\;

Low-Voltage CMOS Octal Buffer

Low-Voltage CMOS Octal D-Type Flip-Flop With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC374A is a high performance, non−inverting octal D−type flip−flop operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS

Description The 74LVC374A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirecti

OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE

DESCRIPTION The 74LVC374A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE)

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

1. General description The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

1. General description The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

1. General description The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

Low-Voltage CMOS Octal Buffer

Low-Voltage CMOS Octal D-Type Flip-Flop With 5 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) The 74LVC374A is a high performance, non−inverting octal D−type flip−flop operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input

OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE

DESCRIPTION The 74LVC374A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE)

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

DESCRIPTION The 74LVC374A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

1. General description The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the

OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS

Description The 74LVC374A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirecti

OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS

Description The 74LVC374A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirecti

OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE

DESCRIPTION The 74LVC374A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE)

Low-Voltage CMOS Octal D-Type Flip-Flop

文件：101.96 Kbytes Page：10 Pages

OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE

Low-Voltage CMOS Octal D-Type Flip-Flop

文件：101.96 Kbytes Page：10 Pages

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

文件：805.79 Kbytes Page：18 Pages

封装/外壳：20-VFQFN 裸露焊盘 功能：标准 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20DHVQFN 集成电路（IC） 触发器

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 功能：标准 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 8BIT 20SO 集成电路（IC） 触发器

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

文件：805.79 Kbytes Page：18 Pages

Low-Voltage CMOS Octal D-Type Flip-Flop

文件：101.96 Kbytes Page：10 Pages

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

文件：805.79 Kbytes Page：18 Pages

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

文件：805.79 Kbytes Page：18 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：633.9 Kbytes Page：21 Pages

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

文件：633.9 Kbytes Page：21 Pages