OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUT(NONINVERTED)

SYNCHRONOUS 4-BIT UP/DOWN COUNTER

SYNCHRONOUS 4-BIT UP/DOWN COUNTER The SN54 /74LS669 is a synchronous 4-bit up/down counter. The LS669 is a 4-bit binary counter. For high speed counting applications, this presettable counter features an internal carry lookahead for cascading purposes. By clocking all flip-flops simultaneousl

OCTAL BUFFER/LINE DRIVERS WITH 3-STATE OUTPUT(NONINVERTED)

Decade and Binary Counters

文件：131.84 Kbytes Page：10 Pages

丝印代码：74LS00；SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates

1 Features 1• Package Options Include: – Plastic Small-Outline (D, NS, PS) – Shrink Small-Outline (DB) – Ceramic Flat (W) – Ceramic Chip Carriers (FK) – Standard Plastic (N) – Ceramic (J) • Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package • Inputs Are TTL C

丝印代码：74LS00；SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates

1 Features 1• Package Options Include: – Plastic Small-Outline (D, NS, PS) – Shrink Small-Outline (DB) – Ceramic Flat (W) – Ceramic Chip Carriers (FK) – Standard Plastic (N) – Ceramic (J) • Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package • Inputs Are TTL C

丝印代码：74LS00；SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates

1 Features 1• Package Options Include: – Plastic Small-Outline (D, NS, PS) – Shrink Small-Outline (DB) – Ceramic Flat (W) – Ceramic Chip Carriers (FK) – Standard Plastic (N) – Ceramic (J) • Also Available as Dual 2-Input Positive-NAND Gate in Small-Outline (PS) Package • Inputs Are TTL C

丝印代码：74LS07；SN74LS07 Hex Buffers and Drivers With Open-Collector High-Voltage Outputs

1 Features 1• Convert TTL Voltage Levels to MOS Levels • High Sink-Current Capability • Input Clamping Diodes Simplify System Design • Open-Collector Driver for Indicator Lamps and Relays 2 Applications • AV Receivers • Audio Docks: Portable • Blu-ray Players and Home Theaters • MP3 P

丝印代码：74LS07；SN74LS07 Hex Buffers and Drivers With Open-Collector High-Voltage Outputs

1 Features 1• Convert TTL Voltage Levels to MOS Levels • High Sink-Current Capability • Input Clamping Diodes Simplify System Design • Open-Collector Driver for Indicator Lamps and Relays 2 Applications • AV Receivers • Audio Docks: Portable • Blu-ray Players and Home Theaters • MP3 P

丝印代码：74LS07；SN74LS07 Hex Buffers and Drivers With Open-Collector High-Voltage Outputs

1 Features 1• Convert TTL Voltage Levels to MOS Levels • High Sink-Current Capability • Input Clamping Diodes Simplify System Design • Open-Collector Driver for Indicator Lamps and Relays 2 Applications • AV Receivers • Audio Docks: Portable • Blu-ray Players and Home Theaters • MP3 P

丝印代码：74LS107A；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

丝印代码：74LS107A；DUAL J-K FLIP-FLOPS WITH CLEAR

Package Options Include Plastic ‘*Small Outline’* Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description The 107 contain two independent JK flip-flops with individual JK, clock, and direct clear inputs. The ‘107 is

丝印代码：74LS109A；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

丝印代码：74LS109A；DUAL JK POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Package Options Include Plastic “Small Outline’ Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs Dependable Texas Instruments Quality and Reliability description These devices contain two independent J-K positive- edge triggered flip-flops. A low level

丝印代码：74LS155A；DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

Applications: Dual 2-to 4-Line Decoder Dual 1-to 4-Line Demuiltiplexer 3-to 8-Line Decoder 1-to 8-Line Demultiplexer Individual Strobes Simplify Cascading for Decoding or Demuitiplexing Larger Words Input Clamping Diodes Simplify System Design Choice of Outputs: Totem Pole (“15

丝印代码：74LS155A；DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

Applications: Dual 2-to 4-Line Decoder Dual 1-to 4-Line Demuiltiplexer 3-to 8-Line Decoder 1-to 8-Line Demultiplexer Individual Strobes Simplify Cascading for Decoding or Demuitiplexing Larger Words Input Clamping Diodes Simplify System Design Choice of Outputs: Totem Pole (“15

丝印代码：74LS156；DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

Applications: Dual 2-to 4-Line Decoder Dual 1-to 4-Line Demuiltiplexer 3-to 8-Line Decoder 1-to 8-Line Demultiplexer Individual Strobes Simplify Cascading for Decoding or Demuitiplexing Larger Words Input Clamping Diodes Simplify System Design Choice of Outputs: Totem Pole (“15

丝印代码：74LS156；DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

Applications: Dual 2-to 4-Line Decoder Dual 1-to 4-Line Demuiltiplexer 3-to 8-Line Decoder 1-to 8-Line Demultiplexer Individual Strobes Simplify Cascading for Decoding or Demuitiplexing Larger Words Input Clamping Diodes Simplify System Design Choice of Outputs: Totem Pole (“15

丝印代码：74LS174；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：74LS174；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：74LS175；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：74LS175；HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

“174, 'LS174, ‘S174 Contain Six Flip-Flops with Single-Rail Outputs ‘175, 'L.S175, ‘S175 Contain Four Flip-Flops with Double-Rail Outputs Three Performance Ranges Offered: See Table Lower Right Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications incl

丝印代码：74LS19A；SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS

Functionally and Mechanically Identical to ‘L813, ‘LS14. and ‘LS132, Respectively Improved Line-Receiving Characteristics P-N-P Inputs Reduce System Loading Excellent Noise Immunity with Typical Hysteresis of 0.8 V description Each circuit functions as a NAND gate or inverter, but beca

丝印代码：74LS19A；SCHMITT-TRIGGER POSITIVE-NAND GATES AND INVERTERS WITH TOTEM-POLE OUTPUTS

Functionally and Mechanically Identical to ‘L813, ‘LS14. and ‘LS132, Respectively Improved Line-Receiving Characteristics P-N-P Inputs Reduce System Loading Excellent Noise Immunity with Typical Hysteresis of 0.8 V description Each circuit functions as a NAND gate or inverter, but beca

丝印代码：74LS240；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS240；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS241；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS241；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS244；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS244；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS244；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS244；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS244；SNx4LS24x, SNx4S24x Octal Buffers and Line Drivers With 3-State Outputs

1 Features 1• Inputs Tolerant Down to 2 V, Compatible With 3.3-V or 2.5-V Logic Inputs • Maximum tpd of 15 ns at 5 V • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers • PNP Inputs Reduce DC Loading • Hysteresis at Inputs Improves Noise Margins 2 Applications • Servers

丝印代码：74LS280；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. 80 mW ‘S280. . . 335 mW descrip

丝印代码：74LS280；9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS

Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Can Be Used to Upgrade Existing Systems using MSI Parity Circuits Typical Data-to-Output Delay of Only 14 ns for “S280 and 33 ns for ‘LS280 Typical Power Dissipation: ‘LS280. 80 mW ‘S280. . . 335 mW descrip

丝印代码：74LS283；4-BIT BINARY FULL ADDERS WITH FAST CARRY

Full-Carry Look-Ahead Across the Four Bits Systems Achieve Partial Look-Ahead Performance with the Economy of Ripple Carry Supply Voltage and Ground on Corner Pins to Simplify P-C Board Layout description The *283 and 'LS283 adders are electrically and functionally identical to the

丝印代码：74LS283；4-BIT BINARY FULL ADDERS WITH FAST CARRY

Full-Carry Look-Ahead Across the Four Bits Systems Achieve Partial Look-Ahead Performance with the Economy of Ripple Carry Supply Voltage and Ground on Corner Pins to Simplify P-C Board Layout description The *283 and 'LS283 adders are electrically and functionally identical to the

丝印代码：74LS373；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

丝印代码：74LS374；OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374) P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and

丝印代码：74LS38；QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS

description These devices contain four independent 2-input NAND buffer gates with open-collector outputs. The open- collector outputs require pull-up resistors to perform correctly. They may be connected to other open- collector outputs to implement active-low wired-OR or active-high wired-A

丝印代码：74LS122；RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

文件：1.44339 Mbytes Page：26 Pages

丝印代码：74LS123；RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

文件：1.44339 Mbytes Page：26 Pages

丝印代码：74LS123；RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

文件：1.44339 Mbytes Page：26 Pages

丝印代码：74LS136；QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS

文件：777.97 Kbytes Page：17 Pages

丝印代码：74LS136；QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS

文件：777.97 Kbytes Page：17 Pages

丝印代码：74LS138；3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

文件：1.28939 Mbytes Page：22 Pages

丝印代码：74LS32；QUADRUPLE 2-INPUT POSITIVE OR GATES

文件：1.38763 Mbytes Page：24 Pages

丝印代码：74LS32；QUADRUPLE 2-INPUT POSITIVE OR GATES

文件：1.38763 Mbytes Page：24 Pages

丝印代码：74LS90；DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS

文件：1.40844 Mbytes Page：25 Pages

丝印代码：74LS92；DECADE, DIVIDE-BY-TWELVE AND BINARY COUNTERS

文件：1.40844 Mbytes Page：25 Pages

Quad 2-Input NAND Gate

General Description This device contains four independent gates each of which performs the logic NAND function.

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

Quad 2-Input NAND Gate

General Description This device contains four independent gates each of which performs the logic NAND function.

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

QUAD 2-INPUT NAND GATE

Low Power Schottky

Quad 2-Input NAND Gate

General Description This device contains four independent gates each of which performs the logic NAND function.

Quad 2-Input NAND Gate?

Quad 2-Input NAND Gate • ESD > 3500 Volts

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATES

QUAD 2-INPUT NAND GATE

QUAD 2-INPUT NAND GATE • ESD > 3500 Volts

Quad 2-Input NAND Gates

Quad 2-Input NAND Gate

Ouadruple 2-input Positive NAND Gates

Quadruple 2-Input NAND Gates

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

Quadruple 2-Input NAND Gates

TRANSISTOR TRANSISTOR LOGIC

Quadruple 2input positive-nand gates

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

Quad 2-Input NAND Gate

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

QUAD 2-INPUT NAND GATE

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

Quad 2-Input NAND Gate

QUADRUPLE 2-INPUT POSITIVE-NAND GATES