Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs

General Description The LCX02 contains four 2-input NOR gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX02 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Fea

包装：卷带（TR） 描述：IC GATE NOR 4CH 2-INP 14SOIC 集成电路（IC） 门和反相器

LOW VOLTAGE CMOS QUAD 2-INPUT NOR GATE WITH 5V TOLERANT INPUTS

DESCRIPTION The 74LCX02 is a low voltage CMOS QUAD 2-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. ■ 5V TOLERANT INPUTS ■ HIGH SPEED : tPD = 4.4ns (MAX.) at VCC = 3V ■ POWER DOWN PROTECTION ON INPUTS AND OUTPUTS ■ SYMMETR

LOW VOLTAGE QUAD 2-INPUT NOR GATE WITH 5V TOLERANT INPUTS AND OUTPUTS

Low-Voltage Quad 2-Input NOR Gate with 5-V Tolerant Inputs and Outputs The TC74LCX02 is a high-performance CMOS 2-input NOR gate. Designed for use in 3.3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. The device is designed for low-voltage (3.3 V)

LOW-VOLTAGE CMOS QUAD 2-INPUT NOR GATE

The MC74LCX02 is a high performance, quad 2–input NOR gate operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74

LOW-VOLTAGE CMOS QUAD 2-INPUT NOR GATE

Low-Voltage CMOS Quad 2-Input NOR Gate With 5 V−Tolerant Inputs The MC74LCX02 is a high performance, quad 2−input NOR gate operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer impr

Low Voltage Quad 2-Input NOR Gate with 5V Tolerant Inputs

General Description The LCX02 contains four 2-input NOR gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LCX02 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Fea