Nine wide Schmitt trigger buffer/line driver; inverting

GENERAL DESCRIPTION The 74HC/HCT9014 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9014 are nine wide Schmitt trigger inverting buffer/line drivers with Schmitt trigger inpu

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

Nine wide Schmitt trigger buffer/line driver

GENERAL DESCRIPTION The 74HC/HCT9015 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT9015 are nine wide Schmitt trigger buffer/line drivers with Schmitt trigger inputs. Th

PLL with band gap controlled VCO

PLL with bandgap controlled VCO

GENERAL DESCRIPTION The 74HCT9046A is a high-speed Si-gate CMOS device. It is specified in compliance with “JEDEC standard no. 7A”. FEATURES • Low power consumption • Centre frequency up to 17 MHz (typ.) at VCC = 5.5 V • Choice of two phase comparators(1): – EXCLUSIVE-OR (PC

PLL with band gap controlled VCO

1. General description The 74HCT9046A. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits

PLL with band gap controlled VCO

1. General description The 74HCT9046A. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits

PLL with bandgap controlled VCO

GENERAL DESCRIPTION The 74HCT9046A is a high-speed Si-gate CMOS device. It is specified in compliance with “JEDEC standard no. 7A”. FEATURES • Low power consumption • Centre frequency up to 17 MHz (typ.) at VCC = 5.5 V • Choice of two phase comparators(1): – EXCLUSIVE-OR (PC

PLL with band gap controlled VCO

PLL with bandgap controlled VCO

GENERAL DESCRIPTION The 74HCT9046A is a high-speed Si-gate CMOS device. It is specified in compliance with “JEDEC standard no. 7A”. FEATURES • Low power consumption • Centre frequency up to 17 MHz (typ.) at VCC = 5.5 V • Choice of two phase comparators(1): – EXCLUSIVE-OR (PC

PLL with band gap controlled VCO

PLL with band gap controlled VCO

PLL with band gap controlled VCO

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：托盘 描述：IC PLL BAND GAP CNTRL VCO 16SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：16-DIP（0.300"，7.62mm） 包装：托盘 描述：IC PLL W/BAND GAP VCO 16-DIP 集成电路（IC） 时钟发生器，PLL，频率合成器

PLL with band gap controlled VCO

IC PLL W/BAND GAP VCO 16-TSSOP