Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked-loop with VCO

The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. • Low power consumption\n• VCO-Inhibit control for ON/OFF keying and for low standby power consumption\n• Centre frequency of up to 17 MHz (typical) at VCC = 4.5 V\n• Choice of three phase comparators:• PC1: EXCLUSIVE-OR\n• PC2: Edge-triggered JK flip-flop\n• PC3: Edge-triggered RS flip-flop\n\n• Ex;

Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked loop with VCO

The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. • Low power consumption\n• VCO-Inhibit control for ON/OFF keying and for low standby power consumption\n• Center frequency up to 17 MHz (typical) at VCC = 4.5 V\n• Choice of three phase comparators:• PC1: EXCLUSIVE-OR\n• PC2: Edge-triggered J-K flip-flop\n• PC3: Edge-triggered RS flip-flop\n\n• Exce;

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC PLL W/VCO 16SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC PLL W/VCO 16-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

Logic

High-Speed CMOS Logic Phase-Locked Loop with VCO

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