Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

1. General description The 74HC393; 74HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on

Dual 4-bit binary ripple counter

Dual 4-bit binary ripple counter

The 74HC393; 74HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on nMR clears the counter stag • Input levels:• For 74HC393: CMOS level\n• For 74HCT393: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000V\n• MM JESD22-A115-A exceeds 200V\n\n• Two 4-bit binary counters with individual clocks\n• Divide by any binary module up to 28 in one packag;

Dual 4-bit binary ripple counter

Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

The 74HC393-Q100; 7474HCT393-Q100 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP. A HIGH on nMR clears the • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C\n\n• Input levels:• For 74HC393-Q100: CMOS level\n• For 74HCT393-Q100: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• MIL-STD-883, method 3015 ;

Dual 4-bit binary ripple counter

1. General description The 74HC393-Q100; 74HCT393-Q100 is a dual 4-stage binary ripple counter. Each counter features a clock input (nCP), an overriding asynchronous master reset input (nMR) and 4 buffered parallel outputs (nQ0 to nQ3). The counter advances on the HIGH-to-LOW transition of nCP.

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DUAL 4BIT BINARY RIPPL 14SOIC 集成电路（IC） 计数器，除法器

封装/外壳：14-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC DUAL 4BIT RIPPLE COUNT 14SSOP 集成电路（IC） 计数器，除法器

Dual 4-bit binary ripple counter

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Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (

Dual 4-bit binary ripple counter

GENERAL DESCRIPTION The 74HC/HCT393 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT393 are 4-bit binary ripple counters with separate clocks (1CP and 2 CP) and master reset (