Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

DUAL DECADE RIPPLE COUNTER

DUAL DECADE RIPPLE COUNTER

Dual decade ripple counter

1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decad

Dual decade ripple counter

1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decad

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

Dual decade ripple counter

The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decade or bi-quinary configuratio • Input levels:• For 74HC390: CMOS level\n• For 74HCT390: TTL level\n\n• Two BCD decade or bi-quinary counters\n• One device can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100y\n• Two master reset inputs to clear each decade counter individually\n• Specified in compliance with JEDEC stand;

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

74HCT390DB - Dual decade ripple counter

Dual decade ripple counter - The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD deca ·Input levels:·For 74HC390: CMOS level\n·For 74HCT390: TTL level;

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

Dual decade ripple counter

1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decad

Dual decade ripple counter

The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decade or bi-quinary configuratio • Input levels:• For 74HC390: CMOS level\n• For 74HCT390: TTL level\n\n• Two BCD decade or bi-quinary counters\n• One device can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100\n• Two master reset inputs to clear each decade counter individually\n• Supply voltage range from 4.5 V to 5.5 V\;

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DUAL DECADE RIPP COUNT 16SOIC 集成电路（IC） 计数器，除法器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC DUAL DEC RIPPLE COUNT 16-SSOP 集成电路（IC） 计数器，除法器