Octal D-type transparent latch; 3-state

GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inputs and outputs on opposite sides of package allowing easy interface with microp

封装/外壳：20-DIP（0.300"，7.62mm） 包装：管件 描述：IC LATCH OCTAL D 3STATE 20DIP 集成电路（IC） 锁存器

Octal D-type transparent latch; 3-state

GENERAL DESCRIPTION The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inputs and outputs on opposite sides of package allowing easy interface with microp

Octal 3-State Noninverting Transparent Latch

Octal 3−State Noninverting Transparent Latch High−Performance Silicon−Gate CMOS The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e

Octal 3-State Noninverting Transparent Latch

Octal 3−State Noninverting Transparent Latch High−Performance Silicon−Gate CMOS The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e

Octal 3-State Noninverting Transparent Latch

Octal 3−State Noninverting Transparent Latch High−Performance Silicon−Gate CMOS The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e

Octal 3-State Noninverting Transparent Latch

Octal 3−State Noninverting Transparent Latch High−Performance Silicon−Gate CMOS The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e