丝印代码：74HC4049D；CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Hex Buffer 74HC4049D: HEX BUFFER/CONVERTER (INVERTING) 74HC4050D: HEX BUFFER/CONVERTER General The 74HC4049D and 74HC4050D are high speed CMOS HEX BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTT

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

High Speed CMOS Logic

Features  Output Drive Capability: 10 LSTTL Loads  Low Input Current: 1μA  Outputs directly interface CMOS, NMOS and TTL  Operating Voltage Range: 2V to 6V  CMOS High Noise Immunity  Function compatible with CD4040B

12-stage binary ripple counter

12-stage binary ripple counter

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

12-stage binary ripple counter

12-stage binary ripple counter

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

12-stage binary ripple counter

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

12-stage binary ripple counter

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-Locked Loop

The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The SL74HC4046 phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain op amp DEMOUT. The comparators have two common sig

CMOS Phase Lock Loop

General Description The MM74HC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and VCO sections. This device contains a low power linear voltage controlled oscillator (VCO), a source follower, and t

Phase-Locked Loop

Phase−Locked Loop High−Performance Silicon−Gate CMOS The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Features • Output Drive Cap

Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked-loop with VCO

GENERAL DESCRIPTION The 74HC/HCT4046A are high-speed Si-gate CMOS devices and are pin compatible with the “4046” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Low power consumption • Centre frequency of up to 17 MHz (typ.) at VCC= 4.5

Phase-locked loop with VCO

1. General description The 74HC4046A; 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits • Low power consumption • VCO-Inhibit control for ON/OFF keying and for low standby power consumption • Center frequency up

Phase-locked loop with VCO

1. General description The 74HC4046A-Q100 is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2.

Phase-locked loop with VCO

1. General description The 74HC4046A-Q100 is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2.

Hex inverting HIGH-to-LOW level shifter

1. General description The 74HC4049 is a hex inverter with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • Overvolta

Hex inverting high-to-low level shifter

GENERAL DESCRIPTION The 74HC4049 is a high-speed Si-gate CMOS device and is pin compatible with the “4049” of the “4000B” series. It is specified in compliance with JEDEC standard no. 7A. The 74HC4049 provides six inverting buffers with a modified input protection structure, which has no diode c

Hex inverting high-to-low level shifter

GENERAL DESCRIPTION The 74HC4049 is a high-speed Si-gate CMOS device and is pin compatible with the “4049” of the “4000B” series. It is specified in compliance with JEDEC standard no. 7A. The 74HC4049 provides six inverting buffers with a modified input protection structure, which has no diode c

Hex inverting HIGH-to-LOW level shifter

1. General description The 74HC4049 is a hex inverter with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • Overvolta

Hex inverting high-to-low level shifter

GENERAL DESCRIPTION The 74HC4049 is a high-speed Si-gate CMOS device and is pin compatible with the “4049” of the “4000B” series. It is specified in compliance with JEDEC standard no. 7A. The 74HC4049 provides six inverting buffers with a modified input protection structure, which has no diode c

Hex inverting HIGH-to-LOW level shifter

1. General description The 74HC4049 is a hex inverter with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2. Features and benefits • Wide supply voltage range from 2.0 V to 6.0 V • Overvolta

12-stage binary ripple counter

文件：762.31 Kbytes Page：19 Pages

12-stage binary ripple counter

封装/外壳：16-VFQFN 裸露焊盘 包装：管件 描述：IC BINARY COUNTER ASYNC 16DHVQFN 集成电路（IC） 计数器，除法器

12-stage binary ripple counter

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC COUNTER 12STAGE BINARY 16SOIC 集成电路（IC） 计数器，除法器

74HC4040DB - 12-stage binary ripple counter

12-stage binary ripple counter

文件：762.31 Kbytes Page：19 Pages

12-stage binary ripple counter

文件：762.31 Kbytes Page：19 Pages

12-stage binary ripple counter

文件：762.31 Kbytes Page：19 Pages

12-stage binary ripple counter

文件：762.31 Kbytes Page：19 Pages