8-bit universal shift register; 3-state

GENERAL DESCRIPTION The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Multiplexed inputs/outputs provide improved bit density • Four operating modes: – s

8-bit universal shift register; 3-state

8-bit universal shift register; 3-state

The 74HC299 is an 8-bit universal shift register with 3-state outputs. It contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mod

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC UNIV SHIFT REGISTER 20TSSOP 集成电路（IC） 通用总线功能

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC UNIV SHIFT REGISTER 20TSSOP 集成电路（IC） 通用总线功能

8-bit universal shift register; 3-state

GENERAL DESCRIPTION The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Multiplexed inputs/outputs provide improved bit density • Four operating modes: – s

8-bit universal shift register; 3-state

GENERAL DESCRIPTION The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Multiplexed inputs/outputs provide improved bit density • Four operating modes: – s

8-bit universal shift register; 3-state

GENERAL DESCRIPTION The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Multiplexed inputs/outputs provide improved bit density • Four operating modes: – s

8-bit universal shift register; 3-state

GENERAL DESCRIPTION The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Multiplexed inputs/outputs provide improved bit density • Four operating modes: – s