Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

Presettable synchronous BCD decade counter; asynchronous reset

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive

Presettable synchronous BCD decade counter; asynchronous reset

1. General description The 74HC160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset H

Synchronous Decade Counter with Asynchronous Clear

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封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC SYNC BCD DECADE COUNTR 16SSOP 集成电路（IC） 计数器，除法器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 包装：管件 描述：IC SYNC BCD DECADE COUNT 16SSOP 集成电路（IC） 计数器，除法器

Presettable synchronous BCD decade counter; asynchronous reset

1. General description The 74HC160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset H

Presettable synchronous BCD decade counter; asynchronous reset

GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Synchronous counting and loading • Two count enable inputs for n-bit cascading • Positive