Bus interface registers

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-t

封装/外壳：轴向 包装：散装 描述：FIXED IND 8.2UH 275MA 1.9 OHM TH 电感器，线圈，扼流圈 固定电感器

色环/插件电感

色环/插件电感

封装/外壳：轴向 包装：散装 描述：FIXED IND 8.2UH 275MA 1.9 OHM TH 电感器，线圈，扼流圈 固定电感器

High Q, high self-resonant frequency Varnish coated

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Bus interface registers

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-t

Bus interface registers

DESCRIPTION The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. FEATURES • High speed parallel registers with positive edge-triggered D-t