Transceivers/Registers

General Description These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate cl

Transceivers/Registers

General Description These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate cl

Transceivers/Registers

文件：188.34 Kbytes Page：10 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TXRX NON-INVERT 5.5V 24SOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TXRX NON-INVERT 5.5V 24SOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Transceivers/Registers

文件：188.34 Kbytes Page：10 Pages

Transceivers/registers

DESCRIPTION The 74F651A and 74F652A transceivers/registers consist of bus transceiver circuits with 3–State outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked

Transceivers/registers

DESCRIPTION The 74F651A and 74F652A transceivers/registers consist of bus transceiver circuits with 3–State outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked

Transceivers/registers

DESCRIPTION The 74F651A and 74F652A transceivers/registers consist of bus transceiver circuits with 3–State outputs, D–type flip–flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked