Octal Registered Transceiver

General Description The 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either directi

Octal registered transceiver, non-inverting 3-State

DESCRIPTION The 74F543 and 74F544 Octal Registered Transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of in

Octal Registered Transceiver

General Description\nThe 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction ■ 8-bit octal transceiver\n■ Back-to-back registers for storage\n■ Separate controls for data flow in each direction\n■ A outputs sink 24 mA, B outputs sink 64 mA;

Octal registered transceiver,inverting (3-State)

Octal Registered Transceiver

文件：186.54 Kbytes Page：10 Pages

Octal Registered Transceiver

General Description The 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either directi

Octal Registered Transceiver

General Description The 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either directi

Octal Registered Transceiver

General Description The 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either directi

Octal Registered Transceiver

文件：186.54 Kbytes Page：10 Pages

Octal Registered Transceiver

文件：186.54 Kbytes Page：10 Pages

Octal Registered Transceiver

文件：186.54 Kbytes Page：10 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TRANSCEIVER INVERT 5.5V 24SOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Octal Registered Transceiver

文件：186.54 Kbytes Page：10 Pages

封装/外壳：24-DIP（0.300"，7.62mm） 包装：管件 描述：IC TRANSCEIVER INVERT 5.5V 24DIP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Octal Registered Transceiver

文件：186.54 Kbytes Page：10 Pages