Octal Serial/Parallel Register with Sign Extend

General Description The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the ris

Octal Serial/Parallel Register with Sign Extend

General Description The ’F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATEÉ parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the r

封装/外壳：20-DIP（0.300"，7.62mm） 功能：串行至并行 包装：管件 描述：IC REGISTER SER/PAR W/EXT 20-DIP 集成电路（IC） 移位寄存器

Octal Serial/Parallel Register with Sign Extend

General Description The ’F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATEÉ parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the r

8-bit serial/parallel register with sign extend 3-State

DESCRIPTION The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the c

Octal Serial/Parallel Register with Sign Extend

General Description The ’F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATEÉ parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the r

8-bit serial/parallel register with sign extend 3-State

DESCRIPTION The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the c