1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

1-of-8 decoder/demultiplexer

DESCRIPTION The 74F138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active low outputs (Q0 – Q7). The device features three enable inputs; two active low (E0, E1) and one active high (E2). Every output will be high unless E0 and

1-of-8 decoder/demultiplexer

1-of-8 Decoder/Demultiplexer

1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

1-of-8 Decoder/Demultiplexer

General Description The F138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three F138 devices or a 1-of-32 decoder using

74系列逻辑芯片

1-of-8 Decoder/Demultiplexer

文件：174.53 Kbytes Page：10 Pages

1-of-8 Decoder/Demultiplexer

文件：174.53 Kbytes Page：10 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DECODER/DEMUX 1X3:8 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC DECODER/DEMUX 1X3:8 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

1-of-8 Decoder/Demultiplexer

文件：174.53 Kbytes Page：10 Pages

1-of-8 decoder/demultiplexer

DESCRIPTION The 74F138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active low outputs (Q0 – Q7). The device features three enable inputs; two active low (E0, E1) and one active high (E2). Every output will be high unless E0 and

1-of-8 decoder/demultiplexer

DESCRIPTION The 74F138 decoder accepts three binary weighted inputs (A0, A1, A2) and when enabled, provides eight mutually exclusive, active low outputs (Q0 – Q7). The device features three enable inputs; two active low (E0, E1) and one active high (E2). Every output will be high unless E0 and