找IC，尽在114IC

芯片资料
  • 芯片资料
  • 丝印反查
  • 库存查询
  • 行业新闻
  • 制造商
  • 替换型号
  • 晶体管

位置：首页 > IC中文资料 > 74ALVC74

74ALVC74价格

参考价格：￥1.5600

型号：74ALVC74BQ 品牌：NXP/PHILIPS 备注：这里有74ALVC74多少钱，2026年最近7天走势，今日出价，今日竞价，74ALVC74批发/采购报价，74ALVC74行情走势销售排行榜，74ALVC74报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74ALVC74

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

PHILIPS

飞利浦

74ALVC74

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

NEXPERIA

安世

74ALVC74BQ

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

PHILIPS

飞利浦

74ALVC74BQ

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

NEXPERIA

安世

74ALVC74D

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

NEXPERIA

安世

74ALVC74D

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data inp • Wide supply voltage range from 1.65 V to 3.6 V\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• 3.6 V tolerant inputs/outputs\n• CMOS low power consumption\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• Power-d;

NEXPERIA

安世

74ALVC74D

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

PHILIPS

飞利浦

74ALVC74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t

PHILIPS

飞利浦

74ALVC74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th

NEXPERIA

安世

74ALVC74PW

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data inp • Wide supply voltage range from 1.65 V to 3.6 V\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• 3.6 V tolerant inputs/outputs\n• CMOS low power consumption\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• Power-d;

NEXPERIA

安世

74ALVC74PW-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74ALVC74-Q100 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.65 V to 3.6 V\n• CMOS low power dissipation\n• Overvoltage tolerant inputs to 3.6 V\n• Direct interface with TTL levels\n• IOFF c;

NEXPERIA

安世

74ALVC74D,112

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器

ETC

知名厂家

74ALVC74D,118

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器

ETC

知名厂家

SN74ALVC74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

文件：127.41 Kbytes Page：8 Pages

TI

德州仪器

SN74ALVC74DGV

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

文件：127.41 Kbytes Page：8 Pages

TI

德州仪器

SN74ALVC74PW

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

文件：127.41 Kbytes Page：8 Pages

TI

德州仪器

74ALVC74产品属性

  • 类型

    描述

  • VCC (V)：

    1.65 - 3.6

  • Logic switching levels：

    TTL

  • Output drive capability (mA)：

    ± 24

  • tpd (ns)：

    2.3

  • fmax (MHz)：

    425

  • Power dissipation considerations：

    low

  • Tamb (°C)：

    -40~85

  • Rth(j-a) (K/W)：

    103

  • Ψth(j-top) (K/W)：

    18.3

  • Rth(j-c) (K/W)：

    71

  • Package name：

    DHVQFN14

74ALVC74供应商更多...

更新时间：2026-7-31 14:24:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
深圳安世裕电子科技有限公司
74ALVC74PW,118
NEXPERIA/安世
23+
NA
9990
只有原装
询价
深圳市纳艾斯科技有限公司
74ALVC74PW/S911
恩XP
24+
TSSOP14
80000
只做自己库存 全新原装进口正品假一赔百 可开13%增
询价
中天科工半导体（深圳）有限公司
74ALVC74PW
恩XP
25+
TSSOP14
26168
NXP/恩智浦全新特价74ALVC74PW即刻询购立享优惠#长期有货
询价
深圳市华高宇电子有限公司
74ALVC74BQ
恩XP
21+
6000
只做原装正品,卖元器件不赚钱交个朋友
询价
深圳市科达星科技有限公司
74ALVC74AMDC
IDT
25+
5500
原装现货,特价销售
询价
深圳市诺美思科技有限公司
74ALVC74PW/S911
恩XP
原厂封装
9800
原装进口公司现货假一赔百
询价
深圳市英科美电子有限公司
74ALVC74PW
恩XP
2223+
TSSOP
26800
只做原装正品假一赔十为客户做到零风险
询价
深圳市豪迈兴电子有限公司
74ALVC74PW118
恩XP
2602+
N/A
25843
公司原厂原装现货假一罚十!特价出售!强势库存!
询价
深圳市欧立现代科技有限公司
74ALVC74D
ph
26+
N/A
6980
原装现货,可开13%税票
询价
深圳市众芯源半导体有限公司
74ALVC74D112
恩XP
25+
DHVQFN-14
10000
原装优势现货
询价

74ALVC74芯片相关品牌

74ALVC74规格书下载地址

74ALVC74参数引脚图相关

74ALVC74数据表相关新闻

DdatasheetPDF页码索引

新数据|IC资料索引|IC关键词|IC库存|IC中文资料|关于我们|联系我们

Copyright © 2003-2026 www.114ic.cn All Rights Reserved 网站备案: 粤ICP备05011613号 粤公网安备 44030402000933号

声明：本站所有资料均来自互联网及网友提供，仅供学习和研究使用，无任何商业目的，版权归原作如有侵权请联系QQ：303638005，本站马上更正

字母索引：ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789

深圳市市场监督管理局企业主体身份公示