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74ALVC74价格

参考价格：￥1.5600

型号：74ALVC74BQ 品牌：NXP/PHILIPS 备注：这里有74ALVC74多少钱，2026年最近7天走势，今日出价，今日竞价，74ALVC74批发/采购报价，74ALVC74行情走势销售排行榜，74ALVC74报价。

型号	功能描述	生产厂家企业	LOGO
74ALVC74	Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t	PHILIPS 飞利浦	PHILIPS
74ALVC74	Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th	NEXPERIA 安世	NEXPERIA
74ALVC74BQ	Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t	PHILIPS 飞利浦	PHILIPS
74ALVC74BQ	Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th	NEXPERIA 安世	NEXPERIA
74ALVC74D	Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th	NEXPERIA 安世	NEXPERIA
74ALVC74D	Dual D-type flip-flop with set and reset; positive-edge trigger The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data inp • Wide supply voltage range from 1.65 V to 3.6 V\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• 3.6 V tolerant inputs/outputs\n• CMOS low power consumption\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• Power-d;	NEXPERIA 安世	NEXPERIA
74ALVC74D	Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t	PHILIPS 飞利浦	PHILIPS
74ALVC74PW	Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on t	PHILIPS 飞利浦	PHILIPS
74ALVC74PW	Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of th	NEXPERIA 安世	NEXPERIA
74ALVC74PW	Dual D-type flip-flop with set and reset; positive-edge trigger The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and complementary Q and Q outputs.\n The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data inp • Wide supply voltage range from 1.65 V to 3.6 V\n• Complies with JEDEC standard:• JESD8-7 (1.65 V to 1.95 V)\n• JESD8-5 (2.3 V to 2.7 V)\n• JESD8B/JESD36 (2.7 V to 3.6 V)\n\n• 3.6 V tolerant inputs/outputs\n• CMOS low power consumption\n• Direct interface with TTL levels (2.7 V to 3.6 V)\n• Power-d;	NEXPERIA 安世	NEXPERIA
74ALVC74PW-Q100	Dual D-type flip-flop with set and reset; positive-edge trigger The 74ALVC74-Q100 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.65 V to 3.6 V\n• CMOS low power dissipation\n• Overvoltage tolerant inputs to 3.6 V\n• Direct interface with TTL levels\n• IOFF c;	NEXPERIA 安世	NEXPERIA
74ALVC74D,112	封装/外壳：14-SOIC（0.154"，3.90mm 宽）功能：设置（预设）和复位包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC）触发器	ETC 知名厂家	ETC
74ALVC74D,118	封装/外壳：14-SOIC（0.154"，3.90mm 宽）功能：设置（预设）和复位包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC）触发器	ETC 知名厂家	ETC
SN74ALVC74	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET 文件：127.41 Kbytes Page：8 Pages	TI 德州仪器	TI
SN74ALVC74DGV	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET 文件：127.41 Kbytes Page：8 Pages	TI 德州仪器	TI
SN74ALVC74PW	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET 文件：127.41 Kbytes Page：8 Pages	TI 德州仪器	TI

74ALVC74产品属性

类型
描述
VCC (V)：
1.65 - 3.6
Logic switching levels：
TTL
Output drive capability (mA)：
± 24
tpd (ns)：
2.3
fmax (MHz)：
425
Power dissipation considerations：
low
Tamb (°C)：
-40~85
Rth(j-a) (K/W)：
103
Ψth(j-top) (K/W)：
18.3
Rth(j-c) (K/W)：
71
Package name：
DHVQFN14

74ALVC74供应商更多...

更新时间：2026-5-21 17:39:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳安世裕电子科技有限公司	74ALVC74PW,118	NEXPERIA/安世	23+	NA	9990	只有原装	询价
标准国际(香港)有限公司	74ALVC74PG	IDT	25+		100	全新原装!优势库存热卖中!	询价
深圳市正纳电子有限公司	74ALVC74PW	恩XP	23+	NA	20094	正纳10年以上分销经验原装进口正品做服务做口碑有支持	询价
深圳市芯球通科技有限公司	74ALVC74D	恩XP	23+	SOP14	9865	原装正品,假一赔十	询价
深圳市科恒伟业电子有限公司	74ALVC74BQ	恩XP	2450+	DHVQFN14	8850	只做原装正品假一赔十为客户做到零风险!!	询价
深圳市英科美电子有限公司	74ALVC74PW	恩XP	2223+	TSSOP	26800	只做原装正品假一赔十为客户做到零风险	询价
深圳市豪迈兴电子有限公司	74ALVC74PW118	恩XP	24+	N/A	25843	公司原厂原装现货假一罚十!特价出售!强势库存!	询价
深圳市福田区绿盛电子商行	74ALVC74D	恩XP	2018+		26976	代理原装现货/特价热卖!	询价
深圳市华斯顿科技有限公司	74ALVC74PW	恩XP	25+23+	TSSOP	43302	绝对原装正品全新进口深圳现货	询价
深圳市恒凯威科技开发有限公司	74ALVC74D,112	恩XP	21+	DHVQFN-14	8080	只做原装,质量保证	询价

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找IC，尽在114IC

74ALVC74价格

74ALVC74产品属性

74ALVC74供应商更多...

74ALVC74芯片相关品牌

74ALVC74规格书下载地址

74ALVC74参数引脚图相关

74ALVC74数据表相关新闻

74AHCU04PW-Q100J

74AHC273PW,118

74AUP1G07GW,125

74AHCT1G125GW Nexperia 20+ 5000 SOT353

74AUP1G08GX只做原装现货绝不虚报

74ALVCH32973ZKER

DdatasheetPDF页码索引