Quad 2-input AND gate

DESCRIPTION The 74ALVC08 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The 74ALVC08 provides the 2-input AND fun

Quad 2-input AND gate

1. General description The 74ALVC08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. Schmitt-trigge

Quad 2-input AND gate

The 74ALVC08 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.\n Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times.\n The 74ALVC08 provides the 2-input AND function. • Wide supply voltage range from 1.65 to 3.6 V\n• 3.6 V tolerant inputs/outputs\n• CMOS low power consumption\n• Direct interface with TTL levels (2.7 to 3.6 V)\n• Power-down mode\n• Latch-up performance exceeds 250 mA\n• Complies with JEDEC standard:\n• JESD8-7 (1.65 to 1.95 V)\n• JESD8-5 (2.3 to 2;

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE AND 4CH 2-INP 14SO 集成电路（IC） 门和反相器

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE AND 4CH 2-INP 14SO 集成电路（IC） 门和反相器

QUADRUPLE 2-INPUT POSITIVE-AND GATE

文件：575.82 Kbytes Page：14 Pages

QUADRUPLE 2-INPUT POSITIVE-AND GATE

文件：575.82 Kbytes Page：14 Pages

QUADRUPLE 2-INPUT POSITIVE-AND GATE

文件：575.82 Kbytes Page：14 Pages

QUADRUPLE 2-INPUT POSITIVE-AND GATE

文件：575.82 Kbytes Page：14 Pages

QUADRUPLE 2-INPUT POSITIVE-AND GATE

文件：575.82 Kbytes Page：14 Pages