Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent d

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device

Dual 2-to-4 line decoder/demultiplexer

The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device has two independent deco • Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC139: CMOS level\n• For 74AHCT139: TTL level\n\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\n• MM EIA/JESD22-A115-A exceeds 200 V\n• CDM EIA/JESD22-;

Dual 2-to-4 line decoder/demultiplexer

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent d

Dual 2-to-4 line decoder/demultiplexer

The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.\n The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device has t • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40°C to +85°C and from -40°C to +125°C\n\n• Balanced propagation delays\n• All inputs have Schmitt-trigger actions\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC139-Q100: CMOS level\n• Fo;

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC DECODER/DEMUX 1X2:4 16TSSOP 集成电路（IC） 信号开关，多路复用器，解码器

Dual 2-to-4 line decoder/demultiplexer

文件：696.89 Kbytes Page：16 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC DECODER/DEMUX 1X2:4 16TSSOP 集成电路（IC） 信号开关，多路复用器，解码器

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent d

Dual 2-to-4 line decoder/demultiplexer

DESCRIPTION The 74AHC/AHCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT139 are high-speed, dual 2-to-4 line decoder/demultiplexers. This device has two independent d

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

文件：98.03 Kbytes Page：14 Pages