Octal D-type transparent latch; 3-state

1. General description The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output wil

Octal Transparent D-Type Latch with 3-State Outputs

The 74AHC573 device is an octal transparent D-type latch with 3-state outputs. The supply voltage can accept any voltage from 2.0V to 5.5V.\nThe output enable OE input is active low. In this case, when latch enable LE input is taken high, the Q outputs follow the data D inputs. When LE input is take • Wide Supply Voltage Range: 2.0V to 5.5V\n\n• Input Accept Voltage Higher than the Supply Voltage\n\n• +8mA/-8mA Output Current\n\n• 3-State Outputs Drive Bus Lines Directly\n\n• -40℃ to +125℃ Operating Temperature Range\n\n• Available in Green SOIC-20 and TSSOP-20 Packages;

Octal D-type transparent latch; 3-state

文件：138.66 Kbytes Page：23 Pages

Octal D-type transparent latch; 3-state

文件：91.69 Kbytes Page：20 Pages

Octal D-type transparent latch; 3-state

1. General description The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output wil

Octal D-type transparent latch; 3-state

1. General description The 74AHC573-Q100; 74AHCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch

Octal D-type transparant latch; 3-state

The 74AHC573-Q100; 74AHCT573-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.\n The 74AHC573-Q100; 74AHCT573-Q100 consists of eight D-type transparent latches featuring separate D-type inp • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have a Schmitt trigger action\n• Common 3-state output enable input\n• Inputs accept voltages higher than VCC\n• Input l;

Octal D-type transparent latch; 3-state

1. General description The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output wil

Octal D-type transparant latch; 3-state

The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.\n The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring separate D-type inputs for each latch a • Balanced propagation delays\n• All inputs have a Schmitt trigger action\n• Common 3-state output enable input\n• Functionally identical to the 74AHC373; 74AHCT373\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC573: CMOS input level\n• For 74AHCT573: TTL input level\n\n• ESD p;

Octal D-type transparent latch; 3-state

1. General description The 74AHC573-Q100; 74AHCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch

Octal D-type transparent latch; 3-state

1. General description The 74AHC573; 74AHCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output wil

Octal D-type transparent latch; 3-state

1. General description The 74AHC573-Q100; 74AHCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch

Octal D-type transparent latch; 3-state

1. General description The 74AHC573-Q100; 74AHCT573-Q100 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch

Octal D-type transparent latch; 3-state

文件：138.66 Kbytes Page：23 Pages

Octal D-type transparant latch; 3-state

Octal D-type transparant latch; 3-state

Octal D-type transparant latch 3-state

文件：732.68 Kbytes Page：19 Pages

封装/外壳：20-VFQFN 裸露焊盘 包装：管件 描述：IC TRANSP LATCH OCTAL D 20DHVQFN 集成电路（IC） 锁存器

Octal D-type transparant latch; 3-state

Octal D-type transparent latch; 3-state

文件：91.69 Kbytes Page：20 Pages

Octal D-type transparent latch; 3-state

文件：138.66 Kbytes Page：23 Pages

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC OCTAL D TRANSP LATCH 20SOIC 集成电路（IC） 锁存器

Octal D-type transparant latch 3-state

文件：732.68 Kbytes Page：19 Pages

Octal D-type transparant latch; 3-state

Octal D-type transparent latch; 3-state

文件：91.69 Kbytes Page：20 Pages

Octal D-type transparent latch; 3-state

文件：138.66 Kbytes Page：23 Pages

Octal D-type transparent latch; 3-state

文件：91.69 Kbytes Page：20 Pages

Octal D-type transparant latch 3-state

文件：732.68 Kbytes Page：19 Pages

Octal D-type transparant latch 3-state

文件：732.68 Kbytes Page：19 Pages

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS

文件：579.3 Kbytes Page：18 Pages

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS

文件：579.3 Kbytes Page：18 Pages