Octal D-type transparent latch; 3-state

DESCRIPTION The 74AHC/AHCT373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

Octal D-type transparant latch; 3-state

1. General description The 74AHC373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC373 consists of eight D-type transparent latches featuring separate D-type inputs for each latc

Octal D-type transparant latch; 3-state

The 74AHC373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC373 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outpu • Balanced propagation delays\n• All inputs have a Schmitt-trigger action\n• Common 3-state output enable input\n• Inputs accepts voltages higher than VCC\n• Functionally identical to the 74AHC573; 74AHCT573\n• Input levels at CMOS input level\n• ESD protection:• HBM EIA/JESD22-A114E exceeds 2000 V\;

Octal D-type transparant latch; 3-state

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC OCTAL D TRANSP LATCH 20SOIC 集成电路（IC） 锁存器

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC OCTAL D TRANSP LATCH 20SOIC 集成电路（IC） 锁存器

Octal D-type transparent latch; 3-state

DESCRIPTION The 74AHC/AHCT373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

Octal D-type transparent latch; 3-state

DESCRIPTION The 74AHC/AHCT373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

Octal D-type transparent latch; 3-state

DESCRIPTION The 74AHC/AHCT373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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