Quad buffer/line driver; 3-state

DESCRIPTION The 74AHC/AHCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

Quad buffer/line driver; 3-state

1. General description The 74AHC126; 74AHCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as

standard-logic

The 74AHC126 provides provides four independent buffer gates with\n3-state outputs. Each buffer has a separate enable pin that when\ndriven with a low logic level places the corresponding output in the\nhigh impedance state. The device is designed for operation with a\npower supply range of 2.0V to

QUADRUPLE 3-STATE BUFFERS OE HIGH

文件：314.19 Kbytes Page：9 Pages

Quad buffer/line driver; 3-state

1. General description The 74AHC126; 74AHCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as

Quad buffer/line driver; 3-state

The 74AHC126-Q100; 74AHCT126-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.\n The 74AHC126-Q100; 74AHCT126-Q100 provides four non-inverting buffer/line drivers with 3-state outputs. The • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Balanced propagation delays\n• All inputs have Schmitt trigger action\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC126-Q100: CMOS level\n•;

Quad buffer/line driver; 3-state

1. General description The 74AHC126; 74AHCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as

Quad buffer/line driver; 3-state

The 74AHC126; 74AHCT126 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.\n The 74AHC126; 74AHCT126 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY • Balanced propagation delays\n• All inputs have Schmitt-trigger action\n• Inputs accept voltages higher than VCC\n• Input levels:• For 74AHC126: CMOS level\n• For 74AHCT126: TTL level\n\n• ESD protection:• HBM JESD22-A114E exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n• CDM JESD22-C101C exceeds;

Quad buffer/line driver; 3-state

DESCRIPTION The 74AHC/AHCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

Quad buffer/line driver; 3-state

DESCRIPTION The 74AHC/AHCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

Quad buffer/line driver; 3-state

1. General description The 74AHC126; 74AHCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as

Quad buffer/line driver; 3-state

1. General description The 74AHC126; 74AHCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as

Quad buffer/line driver; 3-state

DESCRIPTION The 74AHC/AHCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state

文件：715.39 Kbytes Page：16 Pages

封装/外壳：14-VFQFN 裸露焊盘 包装：卷带（TR） 描述：IC BUF NON-INVERT 5.5V 14DHVQFN 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Quad buffer/line driver; 3-state

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC BUFFER NON-INVERT 5.5V 14SO 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Quad buffer/line driver; 3-state

文件：715.39 Kbytes Page：16 Pages

Quad buffer/line driver; 3-state

Quad buffer/line driver; 3-state

文件：715.39 Kbytes Page：16 Pages

Quad buffer/line driver; 3-state

文件：715.39 Kbytes Page：16 Pages

QUADRUPLE 3-STATE BUFFERS OE HIGH

文件：314.19 Kbytes Page：9 Pages

QUADRUPLE 3-STATE BUFFERS OE HIGH

文件：314.19 Kbytes Page：9 Pages

QUADRUPLE 3-STATE BUFFERS OE HIGH

文件：314.19 Kbytes Page：9 Pages

QUADRUPLE 3-STATE BUFFERS OE HIGH

文件：314.19 Kbytes Page：9 Pages

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：98.98 Kbytes Page：18 Pages

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

文件：98.98 Kbytes Page：18 Pages