Hex D-Type Flip-Flop with Master Reset

General Description The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：袋 描述：IC FF D-TYPE SNGL 6BIT 16SOIC 集成电路（IC） 触发器

IC FF D-TYPE SNGL 6BIT 16SOIC

IC FF D-TYPE SNGL 6BIT 16SOIC

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 6BIT 16SOIC 集成电路（IC） 触发器

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.

Hex D Flip?묯lop with Master Reset

The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The device is used primarily as a 6−bit edge−triggered storage register. The information on the D inputs is transferred to storage during the LOW−to−HIGH clock transition. The device has a Master Reset to simultaneously clear all flip−flops.