8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR

DESCRIPTION The 74AC299 is an advanced high-speed CMOS 8-BIT PIPO SHIFT REGISTER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. ■ HIGH SPEED: ■ fMAX = 240MHz (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION: ICC = 8µA(MAX.) at TA=25°C ■ HIGH NOISE I

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 功能：通用 包装：卷带（TR） 描述：IC SHIFT REG 8-BIT PIPO 20-TSSOP 集成电路（IC） 移位寄存器

8-Input Universal Shift/Storage Register

General Description The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins

8-Input Universal Shift/Storage Register

General Description The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins

8-Input Universal Shift/Storage Register

General Description The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins

8?묲nput Universal Shift/Storage Register with Common Parallel I/O Pins

The MC74AC299/74ACT299 is an 8−bit universal shift/storage register with 3−state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip−flop outputs are multiplexed to reduce the total number of package pins. Additional

8?묲nput Universal Shift/Storage Register with Common Parallel I/O Pins

The MC74AC299/74ACT299 is an 8−bit universal shift/storage register with 3−state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip−flop outputs are multiplexed to reduce the total number of package pins. Additional