SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

SYNCHRONOUS DECADE RATE MULTIPLIER

DESCRIPTION 一 The 167 contains asynchronous decade counter and four decoding gates that serve to gate the clock through to the output at a sub- multiple of the clock frequency. The output pulse rate, relative to the clock frequency, is determined by signals applied to the Select (So 一 Ss) input

TTL HD74/HD74S Series