WILMAR??Protective Relays - 700 Series

Several types of Reverse Power Relays are available including relays sensitive to reverse reactive power (KVAR). WILMAR is the leading brand of reverse power relays. Our rugged sealed construction provides con tinuous and reliable operation unaffected by shock, vibration or other severe environmen

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包装：散装 描述：BREADBOARD GENERAL PURPOSE PTH 原型开发，制造品 有孔原型板

包装：散装 描述：BELT CLIP 725 MONITOR 1=10PC 静电控制，防静电，ESD，无尘室产品 配件

Fast Ethernet Cat5e Data Double-Ended Cordset

Product Description Fast Ethernet Cat5e Data Double-Ended Cordset: Male straight D-coded black M12 Railway to male straight D-coded black M12 Railway, shielded, 50 V AC / 60 V DC, 4 A; X-FRNC black cable, 4-wires, 0.34 mm²

T-1 Subminiature Lamps

T-1 Subminiature Lamps T-1 Subminiature Short Type Lamps

RS485, 2 Pr #22 Str TC, PE Ins, OSTC Brd, PVC Jkt, AIA Armor, LSZH Jkt

Product Description RS-485, 2 Pair 22AWG (7x30) Tinned Copper, PE Insulation, Overall Beldfoil®+Tinned Copper Braid(65) Shield, PVC Inner Jacket, Aluminum Interlock Armor, LSZH Outer Jacket

T-1 Subminiature Lamps

T-1 Subminiature Lamps T-1 Subminiature Short Type Lamps

T-1 Subminiature Lamps

T-1 Subminiature Lamps T-1 Subminiature Short Type Lamps

Ultralow-Voltage ETR Controller with On-Chip LCD Driver

Overview The LC723461W and LC723462W are ultralow-voltage electronic tuning microcontrollers that include a PLL that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. This IC includes an on-chip DC-DC converter that can easily create the power supply voltages needed for electroni

T-1 Subminiature Lamps

T-1 Subminiature Lamps T-1 Subminiature Short Type Lamps

OVERLOAD SENSING CONTROLS, 7 1/2 - 400AMPS

Features • Current rating 7.4-400 amps • High reliability: does not switch overload current • Adaptable for AC, DC, single-phase or three-phase applications • Stops nuisance trips: thermal element unaffected by transient current surges • Can be mounted in a remote location • Uses minimum spa

T-1 Subminiature Lamps

T-1 Subminiature Lamps T-1 Subminiature Short Type Lamps

CMOS SyncFIFOTM

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full (AF) a

CMOS SyncFIFOTM

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full (AF) a

CMOS SyncFIFOTM

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full (AF) a

CMOS SyncFIFOTM

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full (AF) a

CMOS SyncFIFOTM

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full (AF) a

CMOS SyncFIFOTM

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full (AF) a

CMOS SyncFIFOTM

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full (AF) a

CMOS SyncFIFOTM

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B • Mailbox bypass register in each direction • Programmable Almost-Full (AF) a

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

CMOS SyncBiFIFOTM 64 x 36 x 2

• Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions • Mailbox bypass Register for each FIFO • Progra

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36

• Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) • 64 x 36 storage capacity FIFO buffering data from Port A to Port B • Mailbox bypass registers in each direction • Dynamic Port B bus sizing of 36 bits (l

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

• Two independent FIFOs (64 X 36 storage capacity each) buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C receives) • Clock frequencies up to 67 MHz (10 ns access time) Free-running clock lines for each port: CLKA, CLKB and CLKC, m

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

• Two independent FIFOs (64 X 36 storage capacity each) buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C receives) • Clock frequencies up to 67 MHz (10 ns access time) Free-running clock lines for each port: CLKA, CLKB and CLKC, m

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

• Two independent FIFOs (64 X 36 storage capacity each) buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C receives) • Clock frequencies up to 67 MHz (10 ns access time) Free-running clock lines for each port: CLKA, CLKB and CLKC, m

CMOS TRIPLE BUS SyncFIFO™ WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

• Two independent FIFOs (64 X 36 storage capacity each) buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C receives) • Clock frequencies up to 67 MHz (10 ns access time) Free-running clock lines for each port: CLKA, CLKB and CLKC, m

CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

• Memory storage capacity: IDT723622 – 256 x 36 x 2 IDT723632 – 512 x 36 x 2 IDT723642 – 1,024 x 36 x 2 • Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs buffering dat

CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

• Memory storage capacity: IDT723622 – 256 x 36 x 2 IDT723632 – 512 x 36 x 2 IDT723642 – 1,024 x 36 x 2 • Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs buffering dat

CMOS BUS-MATCHING SyncFIFO TM 256 x 36, 512 x 36, 1,024 x 36

• Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • Clocked FIFO buffering data from Port A to Port B • Clock frequencies up to 83 MHz (8 ns access time) • IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag

CMOS BUS-MATCHING SyncFIFO TM 256 x 36, 512 x 36, 1,024 x 36

• Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • Clocked FIFO buffering data from Port A to Port B • Clock frequencies up to 83 MHz (8 ns access time) • IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag

CMOS BUS-MATCHING SyncFIFO TM 256 x 36, 512 x 36, 1,024 x 36

• Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • Clocked FIFO buffering data from Port A to Port B • Clock frequencies up to 83 MHz (8 ns access time) • IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag

CMOS BUS-MATCHING SyncFIFO TM 256 x 36, 512 x 36, 1,024 x 36

• Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • Clocked FIFO buffering data from Port A to Port B • Clock frequencies up to 83 MHz (8 ns access time) • IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag

CMOS SyncBiFIFOTM WITH BUS-MATCHING

• Memory storage capacity: IDT723624 – 256 x 36 x 2 IDT723634 – 512 x 36 x 2 IDT723644 – 1,024 x 36 x 2 • Clock frequencies up to 67 MHz (10 ns access time) • Two independent clocked FIFOs buffering data in opposite directions • Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

CMOS SyncBiFIFOTM WITH BUS-MATCHING

• Memory storage capacity: IDT723624 – 256 x 36 x 2 IDT723634 – 512 x 36 x 2 IDT723644 – 1,024 x 36 x 2 • Clock frequencies up to 67 MHz (10 ns access time) • Two independent clocked FIFOs buffering data in opposite directions • Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

CMOS SyncFIFO™512 x 36 1,024 x 36 2,048 x 36

• Storage capacity: IDT723631 - 512 x 36 IDT723641 - 1,024 x 36 IDT723651 - 2,048 x 36 • Supports clock frequencies up to 67 MHz • Fast access times of 11ns • Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock ed

CMOS SyncFIFO™512 x 36 1,024 x 36 2,048 x 36

• Storage capacity: IDT723631 - 512 x 36 IDT723641 - 1,024 x 36 IDT723651 - 2,048 x 36 • Supports clock frequencies up to 67 MHz • Fast access times of 11ns • Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock ed

CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

• Memory storage capacity: IDT723622 – 256 x 36 x 2 IDT723632 – 512 x 36 x 2 IDT723642 – 1,024 x 36 x 2 • Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs buffering dat

CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

• Memory storage capacity: IDT723622 – 256 x 36 x 2 IDT723632 – 512 x 36 x 2 IDT723642 – 1,024 x 36 x 2 • Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) • Two independent clocked FIFOs buffering dat

CMOS BUS-MATCHING SyncFIFO TM 256 x 36, 512 x 36, 1,024 x 36

• Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • Clocked FIFO buffering data from Port A to Port B • Clock frequencies up to 83 MHz (8 ns access time) • IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag

CMOS BUS-MATCHING SyncFIFO TM 256 x 36, 512 x 36, 1,024 x 36

• Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • Clocked FIFO buffering data from Port A to Port B • Clock frequencies up to 83 MHz (8 ns access time) • IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag

CMOS BUS-MATCHING SyncFIFO TM 256 x 36, 512 x 36, 1,024 x 36

• Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • Clocked FIFO buffering data from Port A to Port B • Clock frequencies up to 83 MHz (8 ns access time) • IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag

CMOS BUS-MATCHING SyncFIFO TM 256 x 36, 512 x 36, 1,024 x 36

• Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 • Clocked FIFO buffering data from Port A to Port B • Clock frequencies up to 83 MHz (8 ns access time) • IDT Standard timing (using EF and FF) or First Word Fall Through Timing (using OR and IR flag

CMOS SyncBiFIFOTM WITH BUS-MATCHING

• Memory storage capacity: IDT723624 – 256 x 36 x 2 IDT723634 – 512 x 36 x 2 IDT723644 – 1,024 x 36 x 2 • Clock frequencies up to 67 MHz (10 ns access time) • Two independent clocked FIFOs buffering data in opposite directions • Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

CMOS SyncBiFIFOTM WITH BUS-MATCHING

• Memory storage capacity: IDT723624 – 256 x 36 x 2 IDT723634 – 512 x 36 x 2 IDT723644 – 1,024 x 36 x 2 • Clock frequencies up to 67 MHz (10 ns access time) • Two independent clocked FIFOs buffering data in opposite directions • Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags

CMOS SyncFIFO™512 x 36 1,024 x 36 2,048 x 36

• Storage capacity: IDT723631 - 512 x 36 IDT723641 - 1,024 x 36 IDT723651 - 2,048 x 36 • Supports clock frequencies up to 67 MHz • Fast access times of 11ns • Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock ed

Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 150mA Without External Pass Transistors

Voltage Regulators Adjustable from 2V to 37V at Output Currents Up to 150mA Without External Pass Transistors

HIGH PRECISION VOLTAGE REGULATOR

High precision voltage regulator

Voltage Regulator

VOLTAGE REGULATOR

VOLTAGE REGULATOR

VOLTAGE REGULATOR

Integrated Circuit Precision Voltage Regulator

Precision voltage regulator