128K x 36 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configurations ◆ Supports high system speed: Commercial: – 200MHz 3.1ns clock access time Commercial and Industrial: – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ 3.3V core power supply

128K x 36 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configurations ◆ Supports high system speed: Commercial: – 200MHz 3.1ns clock access time Commercial and Industrial: – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ 3.3V core power supply

128K x 36, 256K x 18 3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

Description The IDT71V35761/781 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write c

3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

文件：972.44 Kbytes Page：21 Pages

3.3V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect

文件：972.44 Kbytes Page：21 Pages