MAX V Device Core

Feature Summary The following list summarizes the MAX V device family features: ■ Low-cost, low-power, and non-volatile CPLD architecture ■ Instant-on (0.5 ms or less) configuration time ■ Standby current as low as 25 µA and fast power-down/reset operation ■ Fast propagation delay and clock-t

MAX V Device Core

Feature Summary The following list summarizes the MAX V device family features: ■ Low-cost, low-power, and non-volatile CPLD architecture ■ Instant-on (0.5 ms or less) configuration time ■ Standby current as low as 25 µA and fast power-down/reset operation ■ Fast propagation delay and clock-t

MAX V Device Core

Feature Summary The following list summarizes the MAX V device family features: ■ Low-cost, low-power, and non-volatile CPLD architecture ■ Instant-on (0.5 ms or less) configuration time ■ Standby current as low as 25 µA and fast power-down/reset operation ■ Fast propagation delay and clock-t

MAX V Device Core

Feature Summary The following list summarizes the MAX V device family features: ■ Low-cost, low-power, and non-volatile CPLD architecture ■ Instant-on (0.5 ms or less) configuration time ■ Standby current as low as 25 µA and fast power-down/reset operation ■ Fast propagation delay and clock-t

5M40ZE64C5N - 可编程逻辑芯片, CPLD, MAX V系列, 40 LE, 64EQFP

The 5M40ZE64C5N is a surface mount Flash Complex Programmable Logic Device IC with 40 logic elements. The MAX® V low power CPLDs offer more density and I/Os per footprint versus other CPLDs. MAX® V device features on-chip flash storage, internal oscillator and memory functionality. With up to 50% ·Instant-on (0.5ms or less) configuration time\n·Fast propagation delay and clock-to-output times\n·Internal oscillator\n·Emulated RSDS output support with a data rate of up to 200Mbps\n·Emulated LVDS output support with a data rate of up to 304Mbps\n·Schmitt triggers enabling noise tolerant inputs;

MAX V Device Core

Feature Summary The following list summarizes the MAX V device family features: ■ Low-cost, low-power, and non-volatile CPLD architecture ■ Instant-on (0.5 ms or less) configuration time ■ Standby current as low as 25 µA and fast power-down/reset operation ■ Fast propagation delay and clock-t

MAX V Device Core

Feature Summary The following list summarizes the MAX V device family features: ■ Low-cost, low-power, and non-volatile CPLD architecture ■ Instant-on (0.5 ms or less) configuration time ■ Standby current as low as 25 µA and fast power-down/reset operation ■ Fast propagation delay and clock-t

MAX V Device Handbook

文件：4.0166 Mbytes Page：166 Pages

MAX V Device Handbook

文件：4.0166 Mbytes Page：166 Pages

CPLD - 复杂可编程逻辑器件 CPLD - MAX V 32 Macro 54 IOs

封装/外壳：64-TQFP 裸露焊盘 包装：托盘 描述：IC CPLD 32MC 7.5NS 64EQFP 集成电路（IC） CPLD（复杂可编程逻辑器件）

封装/外壳：64-TQFP 裸露焊盘 包装：托盘 描述：IC CPLD 32MC 7.5NS 64EQFP 集成电路（IC） CPLD（复杂可编程逻辑器件）

MAX V Device Handbook

文件：4.0166 Mbytes Page：166 Pages

3. DC and Switching Characteristics for MAX V Devices

文件：489.1 Kbytes Page：30 Pages

MAX V Device Handbook

文件：4.0166 Mbytes Page：166 Pages

MAX V Device Handbook

文件：4.0166 Mbytes Page：166 Pages

CPLD - 复杂可编程逻辑器件 CPLD - MAX V 32 Macro 54 IOs