Dual JK Negative Edge-Triggered Flip-Flop

文件：357.71 Kbytes Page：8 Pages

Dual JK Negative Edge-Triggered Flip-Flop

Dual JK Negative Edge-Triggered Flip-Flop

文件：357.71 Kbytes Page：8 Pages

OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS

文件：89 Kbytes Page：5 Pages

DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

文件：90.94 Kbytes Page：5 Pages

DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

文件：77.86 Kbytes Page：5 Pages

DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

DUAL 1-OF-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS

文件：90.94 Kbytes Page：5 Pages

9-BIT PARITY GENERATORS/CHECKERS

文件：99.84 Kbytes Page：5 Pages

9-BIT PARITY GENERATORS/CHECKERS

Dual “J-K” Flip-Flop with Set and Reset

Description The CD54AC112/3A and CD54ACT112/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. The CD54AC112/3A and CD54ACT112/3A are supplied in 16 lead dual-in-line ceramic packages (F suffix).

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays 24-mA Output Drive Current Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Me

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

文件：546.06 Kbytes Page：13 Pages

Dual j-k Flip-Flop with Set and Reset

文件：228.31 Kbytes Page：8 Pages