Dual JK Positive Edge-Triggered Flip-Flop

General Description\nThe ’AC/’ACT109 consists of two high-speed completely in dependent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’AC/’ACT74 data sheet) by connecting ■ ICC reduced by 50%\n■ Outputs source/sink 24 mA\n■ ’ACT109 has TTL-compatible inputs\n■ Standard Military Drawing (SMD)\n   — ’AC109: 5962-89551\n   — ’ACT109: 5962-88534 ;

Dual JK Positive Edge-Triggered Flip-Flop

Dual JK Positive Edge-Triggered Flip-Flop

文件：167.82 Kbytes Page：8 Pages

Dual JK Positive Edge-Triggered Flip-Flop

Dual JK Positive Edge-Triggered Flip-Flop

文件：167.82 Kbytes Page：8 Pages

Dual JK Positive Edge-Triggered Flip-Flop

文件：167.82 Kbytes Page：8 Pages

Dual J-K Flip-Flop with Set and Reset

Description The CD54AC109/3A and CD54ACT109/3A are dual “J-K” flip-flops with set and reset that utilize the Harris Advanced CMOS Logic technology. These flip-flops have independent J, K, Set, Reset and Clock inputs and Q and Q outputs. The CD54AC109/3A and CD54ACT109/3A changes state on the posi

Dual j-k Flip-Flop with Set and Reset

文件：228.31 Kbytes Page：8 Pages