Low Power 8-Bit Register

文件：165.48 Kbytes Page：8 Pages

Low Power 8-Bit Register

Low Power 8-Bit Latch

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

Low Power 8-Bit Register

文件：165.48 Kbytes Page：8 Pages