1.1 Features 1

• Architecture designed for ADAS applications

• Video, image, and gaphics processing support

– Full-HD video (1920 × 1080p, 60 fps)

– Multiple video input and video output

• Dual Arm® Cortex®-A15 microprocessor subsystem

• Up to two C66x floating-point VLIW DSP

– Fully object-code compatible with C67x and

C64x+

– Up to thirty-two 16 × 16-Bit fixed-point multiplies

per cycle

• Up to 2.5MB of on-chip L3 RAM

• Level 3 (L3) and level 4 (L4) interconnects

• Two DDR2/DDR3/DDR3L memory interface

(EMIF) modules

– Supports up to DDR2-800 and DDR3-1066

– Up to 2GB supported per EMIF

• Dual Arm® Cortex®-M4 Image Orocessing Units

(IPU)

• Vision acceleration pac

– Up to four Embedded Vision Engines (EVEs)

• IVA-HD subsystem

• Display subsystem

– Display controller with DMA engine and up to

three pipelines

– HDMI™ encoder: HDMI 1.4a and DVI 1.0

compliant

• 2D-graphics accelerator (BB2D) subsystem

– Vivante® GC320 core

• Video Processing Engine (VPE)

• Dual-core PowerVR® SGX544 3D GPU

• Three Video Input Port (VIP) modules

– Support for up to 10 multiplexed input ports

• General-Purpose Memory Controller (GPMC)

• 2-port gigabit ethernet (GMAC)

• Enhanced Direct Memory Access (EDMA)

controller

• Dual Controller Area Network (DCAN) modules

– CAN 2.0B protocol

• PCI-Express® 3.0 port with integrated PHY

– One 2-lane gen2-compliant port

– or two 1-lane gen2-compliant ports

• Sixteen 32-bit general-purpose timers

• 32-bit MPU watchdog timer

• Ten configurable UART/IrDA/CIR modules

• Four Multichannel Serial Peripheral Interfaces

(McSPI)

• Quad SPI interface

• Five Inter-Integrated Circuit (I2C) ports

• SATA interface

• Eight Multichannel Audio Serial Port (McASP)

modules

• SuperSpeed USB 3.0 dual-role device

• Three high-speed USB 2.0 dual-role devices

• Four Multimedia Card/Secure Digital/Secure Digital

Input Output interfaces ( MMC®/ SD®/SDIO)

• Up to 247 General-Purpose I/O (GPIO) pins

• Real-Time Clock SubSystem (RTCSS)

• Device security features

– Hardware crypto accelerators and DMA

– Firewalls

– JTAG® lock

– Secure keys

– Secure ROM and boot

• Power, Reset, and Clock Management (PRSM)

• On-chip debug with CTools technology

• Automotive AEC-Q100 qualified

• 28-nm CMOS technology

• 23 mm × 23 mm, 0.8-mm pitch, 760-Pin BGA

(ABC)

1.2 Applications

• Mono, Stereo or Tri-Optic Front Camera

– Object detection

– Pedestrian detection

– Traffic sign recognition

– Lane detection and departure warning

– Automatic emergency braking

– Adaptive cruise control

– Forward collision warning

– High beam assist

• LVDS or ethernet surround view

– 2D surround view

– 3D surround view

– Rear object detection

– Parking assist

– Pedestrian detection

– Lane tracking

– Drive recording

• Sensor fusion – vision, radar, ultrasonic, lidar

sensors

– Object data fusion

– Raw data fusion

1.3 Description

TI’s new TDA2x System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to

meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2x family

enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power

and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving

experience.

The TDA2x SoC enables sophisticated embedded vision technology in automobiles by broadest range of

ADAS applications including front camera, park assist, surround view and sensor fusion on a single

architecture.

The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and

floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm®

Cortex®-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for

decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for

rendering virtual views, enable a 3D viewing experience. And the TDA2x SoC also integrates a host of

peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view

systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs)

offloading the vision analytics functionality from the application processor while also reducing the power

footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for

efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor,

including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a

debugging interface for visibility into source code execution.

The TDA2x ADAS processor is qualified according to the AEC-Q100 standard.