Features

• Second Generation SuperWIDE HIGH DENSITY

IN-SYSTEM PROGRAMMABLE LOGIC DEVICE

— 3.3V Power Supply

— User Selectable 3.3V/2.5V I/O

— 24000 PLD Gates / 512 Macrocells

— Up to 256 I/O Pins

— 512 Registers

— High-Speed Global Interconnect

— SuperWIDE Generic Logic Block (32 Macrocells) for

Optimum Performance

— SuperWIDE Input Gating (68 Inputs) for Fast

Counters, State Machines, Address Decoders, etc.

— PCB Efficient Ball Grid Array (BGA) Package Options

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 155 MHz Maximum Operating Frequency

— tpd = 6.5 ns Propagation Delay

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture with Single-

Level Global Routing Pool and SuperWIDE GLBs

— Wrap Around Product Term Sharing Array Supports

up to 35 Product Terms Per Macrocell

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Macrocell Registers Feature Multiple Control

Options Including Set, Reset and Clock Enable

— Four Dedicated Clock Input Pins Plus Macrocell

Product Term Clocks

— Programmable I/O Supports Programmable Bus

Hold, Pull-up, Open Drain and Slew Rate Options

— Four Global Product Term Output Enables, Two

Global OE Pins and One Product Term OE per

Macrocell

Description

The ispLSI 5000VE Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

Outputs from the GLBs drive the Global Routing Pool

GRP) between the GLBs. Switching resources are provided

to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and three extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

The 160 product terms are grouped in 32 sets of five and

sent into a Product Term Sharing Array (PTSA) which

allows sharing up to a maximum of 35 product terms for

a single function. Alternatively, the PTSA can be bypassed

for functions of five product terms or less. The

three extra product terms are used for shared controls:

reset, clock, clock enable and output enable.