64BIT RANDOM ACCESS MEMORY

DESCRIPTION The289isahighspeed64-bitRAMorganizedasa16-wordby4-bitarray.Addressinputarebufferedtominimizeloading,andaddressesarefullydecodedon-chip.

Hex Inverters with Schmitt Trigger Inputs

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DUAL JK FLIP - FLOP

[Signetics]

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION—The’90isa4-stageripplecountercontainingahighspeed flip-flopactingasadivide-by-twoandthreeflip-flopsconnectedasadivideby- fivecounter.ItcanbeconnectedtooperatewithaconventionalBCDoutput patternoritcanbeconnectedtoprovidea50dutycycleoutpu

QUAD 2-INPUT NAND GATE

QUAD2-INPUTNANDGATES

QUAD 2-INPUT NAND GATE

QUAD2-INPUTNANDGATES

QUAD 2-INPUT NAND GATE

QUAD2-INPUTNANDGATES

HEX INVERTER

HEXINVERTER LOWPOWERSCHOTTKY

TRIPLE 3-INPUT AND GATE

TRIPLE3-INPUTANDGATE

TRIPLE 3-INPUT AND GATE

TRIPLE3-INPUTANDGATE

TRIPLE 3-INPUT AND GATE

TRIPLE3-INPUTANDGATE

RETRIGGERABLE MONOSTABLE MULTIVIBRATORS

Thesedctriggeredmultivibratorsfeaturepulsewidthcontrolbythreemethods.Thebasicpulsewidthisprogrammedbyselectionofexternalresistanceandcapacitancevalues.TheLS122hasaninternaltimingresistorthatallowsthecircuitstobeusedwithonlyanexternalcapacitor.Oncetrigge

QUAD 3-STATE BUFFERS

QUAD3-STATEBUFFERS LOWPOWERSCHOTTKY

1-OF-8 DECODER/ DEMULTIPLEXER

TheLSTTL/MSISN54/74LS138isahighspeed1-of-8Decoder/Demultiplexer.Thisdeviceisideallysuitedforhighspeedbipolarmemorychipselectaddressdecoding.Themultipleinputenablesallowparallelexpansiontoa1-of-24decoderusingjustthreeLS138devicesortoa1-of-32decoderusing

Hex Inverter with Schmitt Trigger Inputs

GeneralDescription ThisdevicecontainssixindependentgateseachofwhichperformsthelogicINVERTfunction.Eachinputhashysteresiswhichincreasesthenoiseimmunityandtransformsaslowlychanginginputsignaltoafastchanging,jitterfreeoutput. SupplyVoltage7V InputVoltage7V

TRIPLE 3-INPUT AND GATE

TRIPLE3-INPUTANDGATELOWPOWERSCHOTTKY

8-INPUT MULTIPLEXER

TheTTL/MSISN54/74LS151isahighspeed8-inputDigitalMultiplexer.Itprovides,inonepackage,theabilitytoselectonebitofdatafromuptoeightsources.TheLS151canbeusedasauniversalfunctiongeneratortogenerateanylogicfunctionoffourvariables.Bothassertionandnegationoutpu

4 X 4 REGISTER FILE (With Open-Collector Output)

DESCRIPTION The170contains16highspeed,lowpower,transparentD-typelatchesarrangedasfourwordsoffourbitseach,tofunctionasa4X4registerfile.Separatereadandwriteinputs,bothaddressandenable,allowsimultaneousreadandwriteoperation.

4 X 4 REGISTER FILE (With Open-Collector Output)

DESCRIPTION The170contains16highspeed,lowpower,transparentD-typelatchesarrangedasfourwordsoffourbitseach,tofunctionasa4X4registerfile.Separatereadandwriteinputs,bothaddressandenable,allowsimultaneousreadandwriteoperation.

4 X 4 REGISTER FILE (With Open-Collector Output)

DESCRIPTION The170contains16highspeed,lowpower,transparentD-typelatchesarrangedasfourwordsoffourbitseach,tofunctionasa4X4registerfile.Separatereadandwriteinputs,bothaddressandenable,allowsimultaneousreadandwriteoperation.

PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

TheSN54/74LS192isanUP/DOWNBCDDecade(8421)CounterandtheSN54/74LS193isanUP/DOWNMODULO-16BinaryCounter.SeparateCountUpandCountDownClocksareusedandineithercountingmodethecircuitsoperatesynchronously.TheoutputschangestatesynchronouswiththeLOW-to-HIGHtransitions

4-STAGE PRESETTABLE RIPPLE COUNTERS

4-STAGEPRESETTABLERIPPLECOUNTERS TheSN54/74LS196decadecounterispartitionedintodivide-by-twoanddivide-by-fivesectionswhichcanbecombinedtocounteitherinBCD(8,4,2,1)sequenceorinabi-quinarymodeproducinga50dutycycleoutput.TheSN54/74LS197containsdivide-by-tw

4-STAGE PRESETTABLE RIPPLE COUNTERS

4-STAGEPRESETTABLERIPPLECOUNTERS TheSN54/74LS196decadecounterispartitionedintodivide-by-twoanddivide-by-fivesectionswhichcanbecombinedtocounteitherinBCD(8,4,2,1)sequenceorinabi-quinarymodeproducinga50dutycycleoutput.TheSN54/74LS197containsdivide-by-tw

DUAL 4-INPUT POSITIVE AND GATE

DUAL4-INPUTPOSITIVEANDGATE

DUAL 4-INPUT POSITIVE AND GATE

DUAL4-INPUTPOSITIVEANDGATE

DUAL 4-INPUT POSITIVE AND GATE

DUAL4-INPUTPOSITIVEANDGATE

QUAD 2-INPUT MULTIPLEXER WITH 3-STATE OUTPUTS

QUAD2-INPUTMULTIPLEXERWITH3-STATEOUTPUTS TheLSTTL/MSISN54/74LS257BandtheSN54/74LS258BareQuad2-InputMultiplexerswith3-stateoutputs.FourbitsofdatafromtwosourcescanbeselectedusingaCommonDataSelectinput.Thefouroutputspresenttheselecteddataintrue(non-inverted

DUAL 5-INPUT NOR GATE

DUAL5-INPUTNORGATE

TRIPLE 3-INPUT NOR GATE

TRIPLE3-INPUTNORGATE

TRIPLE 3-INPUT NOR GATE

TRIPLE3-INPUTNORGATE

TRIPLE 3-INPUT NOR GATE

TRIPLE3-INPUTNORGATE

BCD TO 7-SEGMENT DECODER/DRIVER

DESCRIPTION The347isthesameasthe47exceptthattheOutputOFFVoltage,VOH,isspecifiedas7.0Vratherthan15V,withthesameIOHlitmitof250μA.Forallotherinformationpleaserefertothe47datasheet.

BCD TO 7-SEGMENT DECODER/DRIVER

DESCRIPTION The347isthesameasthe47exceptthattheOutputOFFVoltage,VOH,isspecifiedas7.0Vratherthan15V,withthesameIOHlitmitof250μA.Forallotherinformationpleaserefertothe47datasheet.

BCD TO 7-SEGMENT DECODER/DRIVER

DESCRIPTION The347isthesameasthe47exceptthattheOutputOFFVoltage,VOH,isspecifiedas7.0Vratherthan15V,withthesameIOHlitmitof250μA.Forallotherinformationpleaserefertothe47datasheet.

DUAL 4-INPUT NAND BUFFER

DUAL4-INPUTNANDBUFFERLOWPOWERSCHOTTKY

DUAL JK FLIP - FLOP

[Signetics]

4-BIT BINARY FULL ADDER

DESCRIPTION The83Ahighspeed4-bitbinaryfulladderswithinternalcarrylookaheadaccepttwo4-binbinarywords(A0-A3,B0-B3)andaCarryinput(C0).

4-BIT BINARY FULL ADDER

DESCRIPTION The83Ahighspeed4-bitbinaryfulladderswithinternalcarrylookaheadaccepttwo4-binbinarywords(A0-A3,B0-B3)andaCarryinput(C0).

4-BIT BINARY FULL ADDER

DESCRIPTION The83Ahighspeed4-bitbinaryfulladderswithinternalcarrylookaheadaccepttwo4-binbinarywords(A0-A3,B0-B3)andaCarryinput(C0).

64-Bit Random Access Memory(Open Collector)

DESCRIPTION The89isa64-Bithigh-speedRead/WriteRandomAccessMemoryforuseasascratchpadmemorywithnon-destructiveread-out.Memorycellsareorganizedinamatrixtoprovide16wordsoffourbitseach.

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION—The’90isa4-stageripplecountercontainingahighspeed flip-flopactingasadivide-by-twoandthreeflip-flopsconnectedasadivideby- fivecounter.ItcanbeconnectedtooperatewithaconventionalBCDoutput patternoritcanbeconnectedtoprovidea50dutycycleoutpu

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION—The’90isa4-stageripplecountercontainingahighspeed flip-flopactingasadivide-by-twoandthreeflip-flopsconnectedasadivideby- fivecounter.ItcanbeconnectedtooperatewithaconventionalBCDoutput patternoritcanbeconnectedtoprovidea50dutycycleoutpu

The ’90 is a 4-stage ripple counter containing a high speed flip-flop acting as a divide-by-two and three flip-flops connected as a divideby- five counter.

DESCRIPTION—The’90isa4-stageripplecountercontainingahighspeed flip-flopactingasadivide-by-twoandthreeflip-flopsconnectedasadivideby- fivecounter.ItcanbeconnectedtooperatewithaconventionalBCDoutput patternoritcanbeconnectedtoprovidea50dutycycleoutpu

DIVIDE-BY-TWELVE COUNTER

DESCRIPTION- The’92isa4-stageripplecountercontainingahighspeedflip-flopactingasadivide-by-twoandthreeflip-flopsconnectedasadivide-by-six.HIGHsignalsontheMasterReset(MR)inputsoverridetheclocksandforcealloutputstotheLOWstate.

DIVIDE-BY-TWELVE COUNTER

DESCRIPTION- The’92isa4-stageripplecountercontainingahighspeedflip-flopactingasadivide-by-twoandthreeflip-flopsconnectedasadivide-by-six.HIGHsignalsontheMasterReset(MR)inputsoverridetheclocksandforcealloutputstotheLOWstate.

4-BIT RIGHT/LEFT SHIGT REGISTER

Quad 2-Input NAND Gates

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Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NAND Gates

文件：120.38 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

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Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

文件：120.07 Kbytes Page：6 Pages

Quad 2-Input NOR Gates

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Hex Inverting Gates

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These devices contain six independent inverters

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